Magnetoresistive random access memory (MRAM) is a non-volatile random access memory in which data is stored by magnetic storage elements.
A conventional MRAM cell comprises two ferromagnetic plates separated by a thin insulating layer. One of the two plates is a permanent magnet (“fixed layer”) set to a particular polarity while the field of the second plate (“free layer”) can be configured to match that of an external field to store data. This configuration is known as a spin valve and is the simplest structure for an MRAM bit. Such magnetic memory cells may be combined to form a memory device.
Sensing or reading of a magnetic memory cell is accomplished by measuring the electrical resistance of the cell. A particular cell is typically selected by powering an associated transistor that switches current from a bitline through the cell to ground. The electrical resistance of the cell changes due to the spin orientation of the electrons in the two plates of the STT MRAM cell. By measuring the resulting current, the resistance inside any particular cell can be determined. In general, the cell is considered to be a “1” if the two plates have the same polarity and a “0” if the two plates are of opposite polarity and have a higher resistance.
FIG. 1 is an example schematic diagram of a prior art system 10 for sensing a magnetic memory cell 12 such as a Spin Transfer Torque Magnetoresistive Random Access Memory (STT MRAM) cell. The prior art system 10 comprises a plurality of transistors, 14, 16, 18 and 20, a reference current source 22 for providing a reference current 24, a cell current 26, a bitline (BL) control voltage 28, a cell output node 30, a reference output 32 and a mirrored reference current 34. The transistors 14 and 16 may be PMOS transistors, while the remaining transistors 18 and 20 may be NMOS transistors.
In operation, the two pairs of transistors of the prior art sensing system 10 adjust and sense the cell current 26 and the reference current 24 and convert this current difference into a voltage difference between the output nodes 30 and 32. The first pair of transistors 14 and 16 acts as a current mirror while transistors 18 and 20 act as clamp devices for bitline voltage regulation, which may be adjusted by the BL control voltage 28. After the BL control voltage 28 is set, transistors 18 and 20 charge the reference bitline 36 and the cell bitline 38 to a fixed potential which is typically about one threshold voltage of NMOS transistor below BL control voltage 28. The diode connected PMOS transistor 16, which is part of the current mirror, senses the reference current 24 which flows through the NMOS transistor 20. The reference current source 22 is conventionally implemented by an NMOS transistor with accurately controlled gate voltage or by so called reference cells such as preconditioned STT MRAM cells. The reference current 24 is usually set between the current which corresponds to a high current STT MRAM cell state and the current corresponding to a low current STT MRAM cell state. This reference current 24 is mirrored simultaneously by the PMOS current mirror 14, 16 to the cell reference out node 30. The cell current 26 flows through the NMOS transistor 18 to the cell out node 30. If the cell current 26 is higher than the reference current 24, then the cell out voltage 30 is driven to ground. If the cell current 26 is lower than the reference current 24, then the cell out voltage 30 goes up to VDD. The voltage at the reference out node 32 remains fixed at about one threshold voltage of the PMOS transistor 16 below VDD due to the diode connected PMOS 16. The voltage difference between the cell out node 30 and the reference out node 32 is compared and amplified by a subsequent differential latch circuit (not shown) to a full CMOS level.
Two of the main problems with the prior art sensing system 10 are the accuracy of the mirrored reference current, Iref mir 34, and the difference between the bitline voltage 38 and the reference bitline voltage 36 if the difference of the cell currents between a high current cell state and low current cell state of the STT MRAM cell, also known at the read window, is small. These two effects diminish the accuracy of the sense amplifier by resulting in two limiting factors for the read window: the current mirror in the sense amplifier and the devices controlling the bit line voltage which are necessary for the STT MRAM memory cell.
The mismatch of the threshold voltages Vtp of the PMOS transistors 14, 16 in the current mirror leads to a mismatch of the mirrored reference current Iref mir 34 and the reference current Iref 24. The mismatch of the threshold voltages Vtn of the NMOS transistors 18, 20 results in different voltages across the selected STT-MRAM cell 12 and the reference current source 22, which may also be a preconditioned STT-MRAM cell. This voltage difference leads to a current difference between the reference current 24 and the cell current 26 for the same resistances for both paths since the current of an STT MRAM cell is directly proportional to a voltage across it.
Therefore, there exists a need for a system and a method for sensing a magnetic memory cell, such as an STT MRAM, which do not have these disadvantages.